This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-075171, filed on Mar. 17, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing a semiconductor device.
2. Discussion of the Background
A silicon MOS field effect transistor included in semiconductor elements has achieved a high density integration and has increased a driving force at the same time by microminiaturizing the size of an element, in particular, the length of a gate. However, the microminiaturization of the element is limited by physical and economic barriers. Therefore, a technology is required to increase the speed of the semiconductor device and to reduce its power consumption by a method other than microminiaturization.
For this reason, in recent years, a field effect transistor using a semiconductor substrate including an underlying layer having a relaxed SiGe formed on a Si substrate and a strained Si layer thinly formed thereon has been proposed. In this field effect transistor, carriers have high mobility characteristics in the strained Si layer and thus the use of the strained Si layer as a channel region makes it possible to increase the speed of the semiconductor element and to reduce its power consumption.
However, an increase in the concentration of channel impurities in the channel of the field effect transistor for the purpose of preventing a short channel effect thereof results in an increase in the parasitic capacitance of a source/drain diffusion layer. It is known the use of a semiconductor substrate having a SOI structure including a silicon wafer, a silicon oxide layer formed on the silicon wafer, and a semiconductor layer formed on the silicon oxide layer is effective for reducing this parasitic capacitance.
A MOS field effect transistor using a semiconductor substrate having the SOI structure and the strained Si layer is disclosed in Japanese Patent Publication (Laid-Open) No. 1997-321307. Further, a background method of manufacturing a semiconductor device and its structure is disclosed in the Japanese Patent Publication (Laid-Open) No. 1997-321307 and will be described with reference to FIG. 1.
As shown in FIG., 1, a graded SiGe layer 2 is formed on a Si wafer 1 such that the content of Ge gradually increases. Next, a thick stress-relaxed SiGe layer 3 (the content of Ge: 20 atomic % to the extent in which the stress is sufficiently relaxed) is formed on the SiGe layer 2.
Thereafter, oxygen ions are implanted into the stress-relaxed SiGe layer 3 and then the stress-relaxed SiGe layer 3 is annealed at a high temperature (1350xc2x0 C.) to form a buried oxide layer 4 in the stress-relaxed SiGe layer 3.
Next, a thin Si layer is epitaxially grown on the stress-relaxed SiGe layer 3 to form a strained Si layer 5. Further, a field effect transistor having the strained Si layer 5 as a channel region is formed on a semiconductor substrate having such a structure to produce a semiconductor device.
In such a semiconductor device, applying a larger strain to the strained Si layer 5 is more effective to increase the mobility of the carriers in the strained Si layer 5. Further, to apply a larger strain to the strained Si layer 5 in the structure of FIG. 1, it is known the content of Ge of the stress-relaxed SiGe layer 3 needs to be increased to enlarge a difference in a lattice constant between the SiGe and Si.
On the other hand, in order to sufficiently produce the effect of the SOI structure, a uniform, continuous, high-quality buried oxide layer 4 is required. This requires a high-temperature annealing process (1350xc2x0 C.) after the ion implantation of oxygen.
However, SiGe has a property such that an increase in the content of Ge results in a decrease in a melting point. Therefore, when the content of Ge of the stress-relaxed SiGe layer is larger than 20 atomic %, the SiGe layer is melted or oxygen and Ge are vaporized if the SiGe layer is subjected to a high-temperature annealing process. Thus, a uniform, continuous, high-quality buried oxide layer 4 can not be formed.
Also, required is an improvement in a dielectric strength characteristics when a high voltage is applied to a semiconductor device having the above configuration.
Accordingly, one object of the present invention is to solve the above-noted and other problems.
Another object of the present invention is to provide a high-speed, low-power-consumption semiconductor device.
Another object of the present invention is to provide an improved semiconductor device having high dielectric characteristics.
To achieve these and other objects, the present invention provides a novel semiconductor substrate including a SiGe layer in which the content of Ge is increased so as to apply a large strain to a strained Si layer of the surface thereof and a high-quality buried oxide layer and by reducing the parasitic capacitance of a source and a drain diffusion layer by the use of the semiconductor substrate.
According to the method of the present invention, a buried oxide layer is first formed in the first SiGe layer having a low content of Ge. Since the content of Ge of the first SiGe layer is low, even if the buried oxide layer is annealed at a high temperature, the SiGe layer is not melted and oxygen and Ge do not evaporate. Thus, a uniform, continuous, high quality buried oxide layer is produced. Sequentially, a second SiGe layer having a high content of Ge is grown on the first SiGe layer and a strained Si layer is formed thereon. This introduces a large strain into the crystal lattice of the strained Si layer.
Also, the semiconductor device of the present invention has a second SiGe layer having a higher content of Ge grown on the first SiGe layer and a strained Si layer on the second SiGe layer. Therefore, a large strain is applied to the strained Si layer. Further, the first SiGe layer with a low content of Ge has a larger band gap than the second SiGe layer with a high content of Ge. Accordingly, in a field effect transistor with the source region or the drain region facing the first SiGe layer, the elongation of a depletion layer at the pn junction is large and exhibits high dielectric strength characteristics, even if a high voltage is applied to the gate electrode.